The ability to extend a baseline architecture processor functionality through dedicated and specialized hardware functional elements is an important aspect of scaleable and extensible architectures.
One of the preferred methods for extending a baseline architecture processor functionality is through the use of coprocessors. These are dedicated usually single purpose processors that operate at the direction of a processor. One of the traditional uses of coprocessors was as math coprocessors to selectively provide floating point capabilities to architectures that did not directly support such. Some example of such math coprocessors are the Intel 8087 and 80287. Some other potential uses or types of coprocessors include: multiply-accumulators, modulator/demodulators (modems), digital signal processors (DSP), vitturbi calculators, cryptographic processors, image processors, and vector processors.
There have been two different approaches to coprocessors. On the one hand, the floating point unit for the Digital Equipment Corporation (DEC) PDP-11 family of computers was very tightly coupled to its primary processor. One problem that arose is that this tightly coupling required the primary processor to know a substantial amount about the operation of the coprocessor. This complicates circuit design to such an extent that addition of a new coprocessor into an integrated system is a major engineering problem.
The alternative implementation has been to loosely couple the coprocessor to the primary processor. This did have the advantage of abstracting and isolating the operation of the coprocessor from the primary processor, and thus substantially lessening the effort required to integrate a new coprocessor with an existing processor. However, this invariably came at a price. Loss of performance is one problem of this approach. One problem with taking the type of performance hit resulting from this loose coupling is that the break-even point for invoking such a coprocessor is increased correspondingly. Thus, many otherwise attractive applications for coprocessors are not cost effective. Additionally, such an approach often requires use of a bus, with all of the corresponding additional circuitry and chip area.
It is thus important to have a coprocessor interface that is tightly coupled enough that usage of the interface is fast enough that invoking even fairly simple functions is advantageous, while abstracting the interface to such an extent that the processor architecture is isolated from as many of the details of any given coprocessor as possible. Part of this later includes making the interface programmer friendly in order to facilitate tailoring new coprocessor applications in software instead of in hardware